Principal Engineer- DEG Layout
Core
Lead layout design and development for critical analog, mixed-signal, custom digital blocks, standard cells, and full chip levels.
Role type
Principal IC Layout Engineer
Builds
Custom digital blocks, standard cells, and full chip layouts for memory and storage solutions
Domain
Semiconductor / IC Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Analog layout, mixed-signal layout, custom digital block layout, standard cell design, full chip layout, LVS verification, DRC verification, Antenna check, Shield design, Matching analysis, Latch-up analysis, EM/IR/Totem checks, Auto placement, Auto routing, Skill coding, Automation, AI for layout optimization
Preferred skills
Leadership in planning and scheduling, Team mentoring, Cross-functional communication
Technologies
Auto placement tools, Auto routing tools, LVS/DRC verification tools
Responsibilities
Perform layout verification including LVS, DRC, Antenna, Shield, Matching, Latch up, EM IR Totem checks, and quality documentation; Develop digital block layouts using auto placement and route tools; Reduce layout effort by implementing AI solutions; Guide team members in sub-block-level layout execution and review their work; Demonstrate leadership in planning, area/time estimation, scheduling, and delegation to meet project schedules.
