Principal Design Verification Quality Engineer
Core
Lead technical verification approaches to strengthen DRAM verification quality, standardization, and traceability; invent intelligent verification workflows and scalable verification systems.
Role type
Principal Design Verification Quality Engineer
Builds
Scalable verification systems and AI-enabled workflows for DRAM products
Domain
Semiconductor / Memory (DRAM)
Deliverable
production ML models
Required skills
DRAM verification, VLSI fundamentals, digital/analog verification methodologies, testbench development, stimulus generation, debug, Linux environments, EDA tools (Cadence Virtuoso), AI/ML/LLM tools, requirements management (JAMA), automation scripting (Python, Perl, Tcl)
Preferred skills
Mentoring engineers, structured documentation workflows, analog/digital verification testbench development, SystemVerilog, UVM, SpectreFx, PrimeSim
Technologies
SystemVerilog, UVM, SpectreFx, PrimeSim, Cadence Virtuoso, JAMA, JIRA, Python, Perl, Tcl
Responsibilities
Define and drive DRAM verification methodology, quality standards, and AI-enabled strategies; Lead closed-loop silicon learning by identifying verification gaps; Own and continuously improve the JAMA requirements framework; Simplify and optimize verification workflows through automation and AI; Partner across engineering teams to drive methodology decisions.
Seniority
Principal, hands-on IC with strategic leadership
