Design Verification Engineer
Core
Deliver performant and functionally accurate silicon for high-performance GenAI products across compute, memory management, and high-speed connectivity.
Role type
Senior IC silicon verification engineer
Builds
High-performance and sustainable GenAI silicon
Domain
Semiconductor hardware design and verification for AI accelerators
Deliverable
production ML models
Required skills
SystemVerilog, Python, C/C++, Bluespec, UVM, assertion-based verification (ABV), formal verification, simulated verification, silicon micro-architecture knowledge, high-speed connectivity expertise, memory management expertise
Preferred skills
Emulation and prototyping platform experience, silicon debug and bring-up experience
Technologies
SystemVerilog, Python, C/C++, Bluespec, UVM
Responsibilities
Contribute to scalable verification methodology across blocks, subsystems, and full-chip; Own verification execution at subsystem and chip-level including testbench creation; Plan and drive reviews on verification test plans and closure towards silicon milestones
Seniority
Senior, hands-on IC
