Sr. Design Verification Engineer
Core
Develop robust, scalable verification environments for highly complex ASIC and SoC designs to ensure they work exactly as intended.
Role type
Senior IC ASIC Design Verification Engineer
Builds
Verification environments, testbenches, and simulation infrastructure for next-generation memory products
Domain
Semiconductor / Memory / SoC Design
Deliverable
production ML models | product features
Required skills
UVM, SystemVerilog, constrained-random verification, Python, debugging complex functional issues, coverage closure
Preferred skills
mixed-signal verification, DRAM protocol, AI-assisted verification tools, applying AI/ML to verification flows
Technologies
UVM, SystemVerilog, Python, AI-assisted workflows
Responsibilities
Develop and maintain UVM-based SystemVerilog verification environments; Define and execute block and system-level verification plans; Build and enhance Python-based testbenches and simulation infrastructure; Debug complex functional and integration issues; Drive coverage closure and improve verification quality metrics; Explore and adopt AI-assisted techniques to improve productivity
Seniority
Senior, hands-on IC
