Lead DFT Engineer (Edge Computing)
Core
Architecting end-to-end Design for Test (DFT) strategies for complex SoCs to ensure manufacturability, reliability, and power efficiency in edge computing applications.
Role type
Lead DFT Engineer (Edge Computing)
Builds
Data center chips for edge deployment
Domain
Semiconductor design / Edge Computing
Deliverable
production ML models
Required skills
Hierarchical DFT, Scan compression, Boundary Scan, MBIST, In-System Test (IST), Power-on Self-Test (POST), ATPG, IJTAG, FinFET node design, Low-power DFT
Preferred skills
Leadership in DFT, Collaboration with Physical Design and Yield teams
Technologies
Synopsys TestMAX, Siemens/Mentor Tessent, Cadence Modus
Responsibilities
Define and implement end-to-end DFT architecture for complex SoCs; Develop strategies for In-System Test (IST) and power-on self-test (POST); Oversee scan insertion, ATPG, and Memory/Logic BIST; Collaborate with Design, Physical Design, and Yield teams; Lead the bring-up and debug phase on ATE to root-cause silicon failures.
Seniority
Lead, 12+ years experience with 2+ years in leadership
