Senior/Staff Design Verification Engineer, HBM
Core
Verify functionality, performance, and quality of next-generation High Bandwidth Memory (HBM) and DRAM circuits for AI/ML applications, ensuring robust production-ready designs for complex, high-density chips.
Role type
Senior/Staff Design Verification Engineer (Mixed-Signal/Digital)
Builds
Custom digital and RTL2GDS flows for Heterogeneous Integration Group (HIG) HBM solutions
Domain
Semiconductor / Memory / AI & Machine Learning
Deliverable
production ML models | product features
Required skills
Mixed-signal and digital verification methodologies, SystemVerilog (SVA), Full-chip and block-level circuit evaluation, Verification environment development, Functional coverage analysis, Debugging and root-cause analysis, Simulation tools expertise
Preferred skills
Analog and digital simulation tools (HSPICE, Verilog-HDL, FINESIM), Scripting (Python, Perl), Technical leadership and mentoring, AI-enabled verification planning
Technologies
SystemVerilog, SVA, HSPICE, Verilog-HDL, FINESIM, Python, Perl, DDR5, LPDDR5
Responsibilities
Evaluate full-chip and block-level HBM and DRAM circuit designs to ensure functional correctness and performance; Develop verification plans from functional specifications in collaboration with architects and design teams; Create, enhance, and maintain verification environments, testbenches, test vectors, and regressions; Increase functional coverage across DRAM architectures and features using appropriate verification tools and methodologies; Debug design issues, support root-cause analysis, track bugs, and drive coverage and closure; Apply mixed-signal and digital verification techniques using industry-standard simulation tools; Lead verification efforts on assigned projects and mentor verification engineers who are developing their skills
Seniority
Senior/Staff, hands-on IC with mentorship responsibilities