Sr/Staff Design Verification Engineer, HBM Verification Architecture
Core
Develop and implement modular, scalable verification solutions for next-generation High Bandwidth Memory (HBM) DRAM products used in AI and ML applications.
Role type
Senior IC design verification engineer (HBM architecture)
Builds
Custom digital and RTL2GDS flows for 2.5D & 3D package integration
Domain
Semiconductor / Memory / AI & ML infrastructure
Deliverable
production ML models
Required skills
Testbench architecture, SoC-level verification, IP-level verification, 2.5D & 3D package integration, Verilog, FastSpice, mixed-signal verification, pre-silicon/post-silicon debugging, custom design verification
Preferred skills
JEDEC specifications (HBM), verification flow improvement, patent/publication experience
Technologies
Verilog, FastSpice, TSV, RTL2GDS
Responsibilities
Develop verification plans and architecture collateral for IP and SoC levels; Support co-verification of overall systems and customer interactions; Build and improve verification methodology components and GenAI applications; Evaluate and debug pre-silicon and post-silicon issues
Seniority
Senior, hands-on IC