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Lead Principal Engineer, Design Verification

Hyderabad, Telangana, IndiaFull-time2026-05-27 → 2026-10-16

Core

Lead and manage a Design Verification team to ensure delivery of verification achievements and project commitments for complex IC designs.

Role type

Lead Principal Design Verification Engineer

Builds

Memory and storage ICs (DRAM, NAND, NOR)

Domain

Semiconductor / Memory and Storage

Required skills

Design Verification strategy and architecture, Functional/Timing/Mixed-signal verification, SystemVerilog and UVM, CMOS circuit design fundamentals, Digital and analog simulation tools, Team leadership and mentoring, Project management

Preferred skills

Memory related field experience, Debugging complex functional and timing issues, Continuous improvement of verification methodologies and flows

Technologies

Verilog, SystemVerilog, HSPICE, PrimeSim, FineSim, UVM