Synthesis Engineer
Core
Develop digital ASIC designs for Ericsson's 5G/6G mobile network infrastructure, focusing on the final critical stage before fabrication.
Role type
Senior IC ASIC Synthesis Engineer
Builds
High-quality digital ASICs for telecom network infrastructure
Domain
Semiconductors / Telecom / 5G/6G
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
ASIC synthesis, Static Timing Analysis (STA), timing sign-off, power optimization, EDA tool proficiency, scripting (Python, TCL, Linux Shell), low-power design (UPF), RTL2GDS flows
Preferred skills
Multi/Many-Core CPU architectures, Clear Case, Git, Spyglass, floor planning, physical implementation
Technologies
Synopsys Design Compiler, Fusion Compiler, PrimeTime, ICC2, Innovus, Formality/LEC, Python, Perl, TCL, Linux Shell, UPF, VHDL, System Verilog
Responsibilities
Engage in backend development tasks including synthesis, constraints development, equivalence checking, and place-and-route. Run Static Timing Analysis and optimize timing/area/power. Develop scripts to automate processes. Drive innovations in low-power design. Collaborate with cross-functional teams.
Seniority
Senior, hands-on IC