Senior Analog IC Layout Engineer

Dresden, DE (primary site)Full-time2026-10-27 → 2026-11-10

On-site

Core

Implement high-quality analog and mixed-signal layouts and drive full-chip physical integration for CapRAM-based AI hardware.

Role type

Senior IC layout engineer (analog/mixed-signal)

Builds

AI hardware accelerators using proprietary CapRAM technology

Domain

Semiconductor / Analog IC design

Deliverable

production ML models

Required skills

Analog/mixed-signal layout design, CMOS layout principles, physical verification (DRC/LVS/ERC/EM/IR-drop), floorplanning, power distribution networks, signal integrity optimization, tape-out sign-off

Preferred skills

FinFET technology, layout automation scripting (SKILL/Tcl/Python), large-scale mixed-signal integration

Technologies

Cadence Virtuoso, Synopsys Custom Compiler, FD-SOI, high-voltage BCD, multi-layer interconnect

Responsibilities

Implement precision analog/mixed-signal layouts with advanced matching techniques; perform full-chip integration including block placement and routing; optimize for parasitics and noise isolation; execute physical verification and resolve violations; collaborate on floorplanning and integration requirements; support post-layout verification and tape-out

Seniority

Senior, hands-on IC

About Semron

At SEMRON, we’re redefining what’s possible in AI hardware. Our core innovation lies in analog in-memory computing for deep neural network acceleration, enabling us to build compute architectures that scale vertically into the third dimension, much like NAND flash revolutionized memory. This leap in physical density allows us to deploy models with billions of parameters on chip areas as small as a few square millimeters.