Sr Staff CAD Engineer
Core
Develop next-generation automated design flow and add-on tools for physical verification, SOC integration, and tape-out support in semiconductor manufacturing.
Role type
Sr Staff IC CAD/EDA Engineer (Physical Verification & Design Flow)
Builds
Automated physical verification flows, design rule decks, layout migration scripts, and validation procedures for digital and analog ICs.
Domain
Semiconductor / IC Design / Physical Verification
Required skills
CAD and EDA tool development, Physical verification debugging, Design flow optimization, Scripting (Tcl, Perl, Python), Tool integration, Foundry interface management, Validation procedure creation, Documentation and training
Preferred skills
Mentor Calibre svrf/tvf, Synopsys ICV, Full custom layout tools, 3rd party IP onboarding
Technologies
Calibre, ICV, Tcl, Perl, Python, Cadence, Synopsys, Mentor Graphics
Responsibilities
Develop run sets for nanotechnology and support physical verification debugging; Automate and support 3rd party IP onboarding; Integrate EDA tools into cohesive design flows; Define and optimize design methodologies from physical verification to tapeout; Monitor and optimize tool performance; Create comprehensive documentation and training materials.
Seniority
Sr Staff, hands-on IC with leadership and mentorship
