DFT Engineer
Core
Define and implement DFT architectures and logic for complex SoC designs to ensure testability throughout the hardware lifecycle.
Role type
DFT Engineer (SoC Design)
Builds
Custom silicon chips for AWS infrastructure (e.g., Nitro, Graviton, Trainium)
Domain
Semiconductor / Custom Silicon / Cloud Infrastructure
Deliverable
production ML models | product features
Required skills
RTL design (Verilog/SystemVerilog), DFT architecture definition, MBIST, JTAG/TAP, boundary scan, gate-level simulation, UVM-based verification, coverage-driven verification
Preferred skills
Synopsys DFT Compiler, Tessent, memory repair flows, FPGA/emulator environments, advanced scripting (Perl/Tcl/Python), end-to-end chip development
Technologies
Verilog, SystemVerilog, UVM, Perl, Tcl, Python, Synopsys DFT Compiler, Tessent, MBIST, JTAG, IEEE 1149.1
Responsibilities
Define and implement DFT architectures for complex SoC designs; Develop and integrate DFT logic including MBIST, JTAG/TAP, and boundary scan; RTL coding and debug of DFT controllers and infrastructure; Drive gate-level simulations to validate DFT functionality and test patterns; Develop and verify DFT logic using UVM-based testbenches and coverage-driven verification; Participate in design reviews, DFT sign-off processes, and tapeout preparation
Seniority
Mid-Senior, hands-on IC
