Senior Engineer -DFT
Core
Architect, implement, and validate innovative DFT techniques on ARM SoCs; insert DFT logic at RTL and Synthesis gate levels; generate ATE targeted test patterns.
Role type
Senior IC DFT Engineer
Builds
ARM SoC designs with embedded DFT logic and test patterns
Domain
Semiconductor / SoC Design / Digital Test
Required skills
Scan compression and insertion, Memory BIST and repair, Logic BIST, JTAG/IJTAG, at-speed test, ATPG, fault simulation, back-annotated gate level verification, silicon debug, Verilog RTL, TCL, Perl, Unix/Linux
Preferred skills
IEEE 1149/1500/1687/1838 standards, Synthesis & Static Timing Analysis, multi-clock domain and low power design, Siemens DFT tools, Arm IP (Cortex, Mali, AMBA, CoreLink, CoreSight), 2.5D and 3D test, Siemens/Cadence/Synopsys tools
Technologies
Verilog, TCL, Perl, Unix/Linux, Siemens, Cadence, Synopsys, ARM Cortex, Mali, AMBA, CoreLink, CoreSight
Responsibilities
Insert DFT logic into SoC style designs at RTL and Synthesis gate levels; validate all DFT features; generate ATE targeted test patterns; collaborate with front-end design and verification teams on RTL insertion; collaborate with back-end synthesis, place-and-route, and static-timing-analysis teams on gate level insertion and timing closure; work with Test and Debug teams on silicon characterization and validation
Seniority
Senior, hands-on IC (via careerplan.io/jobs/100158973920-senior-engineer-dft-at-arm)
