DFT Engineer
Core
Architect, implement, and validate Design for Test (DFT) techniques on test-chips and hard-macros to prove Arm's soft IP power, performance, area, and functionality within a SoC context.
Role type
DFT Engineer
Builds
DFT logic inserted into SoC designs at RTL and gate levels, ATE-targeted test patterns, and silicon characterization data.
Domain
Semiconductor / SoC Design / Digital Logic
Required skills
Verilog RTL, TCL, Perl, Unix/Linux, Scan compression, Memory BIST, Logic BIST, JTAG/IJTAG, ATPG, fault simulation, back-annotated gate level verification, silicon debug
Preferred skills
IEEE 1149/1500/1687/1838 standards, Synthesis & Static Timing Analysis, SoC multi-clock domain architectures, Siemens DFT tools, Arm IP (Cortex, Mali, AMBA, CoreLink, CoreSight), 2.5D/3D test
Technologies
Verilog, TCL, Perl, Unix/Linux, Siemens, Cadence, Synopsys
Responsibilities
Insert DFT logic into SoC style designs at RTL and Synthesis gate levels; generate ATE targeted test patterns; collaborate with RTL, Verification, Physical Implementation, and Test teams across the project lifecycle from investigation to tape-out and silicon test. (via careerplan.io/jobs/100158931088-dft-engineer-at-arm)
Seniority
Mid-level (2-5 years experience)
