DFT Design Engineer, Machine Learning Acceleration
Core
Design and optimize hardware for AWS custom machine learning inference and training servers (Inferentia and Trainium) by developing advanced Design for Test (DFT) architectures.
Role type
Senior IC ASIC DFT Design Engineer
Builds
Custom SoCs for machine learning data centers
Domain
Semiconductor hardware design / Machine Learning Infrastructure
Deliverable
production ML models
Required skills
DFT architecture design, ATPG, JTAG, MBIST, RTL coding (Verilog/System Verilog), silicon debug, automation scripting
Preferred skills
STA constraints for DFT, gate-level simulation with SDF, Perl/Python/Tcl scripting, yield optimization
Technologies
Verilog, System Verilog, Perl, Python, Tcl, SDF
Responsibilities
Define state-of-the-art DFT architectures for advanced technology nodes, collaborate with block designers and physical design teams, perform RTL coding and verification, create high-coverage test patterns, participate in silicon debug efforts
Seniority
Senior, hands-on IC
