Package Layout Design Staff/Senior Staff Engineer
Core
Develop advanced microelectronic packages for high-speed ICs, managing design from concept through tapeout to ensure performance, reliability, and manufactability.
Role type
Senior IC package layout engineer
Builds
Advanced microelectronic packages for high-speed data infrastructure
Domain
Semiconductor / Advanced Packaging
Required skills
IC package layout tools (Cadence APD, Siemens Xpedition), high-speed interface constraints, power plane design, substrate design rules, 2D/2.5D packaging architectures, thermal/mechanical constraints, NPI support, cross-functional collaboration
Preferred skills
ASIC physical design optimization, tool/process flow development, scripting for automation, CoWoS/EMIB/CPO knowledge
Technologies
Cadence APD, Siemens Xpedition (XPD), CoWoS-S/R/L, EMIB, CPO, CPC
Responsibilities
Drive package development from concept to tapeout, select appropriate technologies, collaborate with substrate suppliers and OSATs, optimize die floorplan for package integration, support NPI from concept to production
Seniority
Senior, hands-on IC
