Analog Layout Principal Engineer
Core
Design and develop complex analog, mixed-signal, and custom layouts independently using Cadence Virtuoso across advanced nodes (deep sub-micron, FinFET, GAA) for Marvell's Central Engineering business group.
Role type
Principal Analog Layout Engineer
Builds
High-speed analog and mixed-signal IP blocks for Automotive, Storage, Security, and Networking
Domain
Semiconductor / Analog IC Design
Required skills
Analog layout design, Mixed-signal layout, EDA tools (Cadence Virtuoso), DRC/LVS/ERC verification, EM/IR optimization, Parasitic management, Floor planning, Tapeout ownership, Device matching, Clock routing, Power routing, Reliability analysis (ESD, latch-up)
Preferred skills
Experience with GAA nodes, Knowledge of layout flows and methodologies, Ability to lead technical discussions and mentorship
Technologies
Cadence Virtuoso, Deep sub-micron nodes, FinFET, GAA
Responsibilities
Drive end-to-end physical verification and resolve violations, Own layout planning from floor planning to tapeout, Coordinate across design, verification, package, and implementation teams, Lead technical discussions and layout reviews, Act as key interface between layout and design teams, Represent the layout team in cross-functional forums
Seniority
Principal, hands-on IC with strategic leadership
