Design Verification - Intern
Core
Intern role focused on developing and verifying next-generation network switch architectures and IPs.
Role type
Design Verification Intern
Builds
Next-generation network switches and switching product IPs
Domain
Semiconductor / Networking / Hardware Design
Required skills
System Verilog, UVM, Python, C++, object-oriented programming, digital logic, random verification techniques, coverage analysis, scripting for automation
Preferred skills
BS/MS in CS/EE, 2+ years before graduation, problem-solving ability
Technologies
System Verilog, UVM, Python, C++, AI tools
Responsibilities
Implement new features in design and verification, write verification test plans, develop random verification environments, create and tune tests for coverage goals, debug simulation failures, analyze code and functional coverage, automate repetitive tasks using scripting
Seniority
Intern
