Package Design Principal Engineer
Core
Lead the development of advanced microelectronic packages from concept through tapeout, optimizing for high-speed interface performance, reliability, and manufactability.
Role type
Principal IC Package Design Engineer
Builds
Advanced IC packages (2D, 2.5D, CoWoS, EMIB) for data infrastructure, enterprise, cloud, and AI systems
Domain
Semiconductor / Advanced Packaging / High-Speed Electronics
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
C4 and BGA ball map development, netlist mapping across dies/interposers/substrates, die placement and padstack definition, Package Requirement Document (PRD) creation, SI/PI fundamentals, 2D/2.5D packaging architecture knowledge, thermal/mechanical constraint analysis, foundry design rule adherence, cross-functional co-design collaboration
Preferred skills
Signal and power simulation interpretation, tool/process/flow development, library maintenance, scripting for automation
Technologies
Cadence OrbitIO, Cadence Integrity System Planner (ISP)
Responsibilities
Develop C4 and BGA ball maps optimized for SI/PI and layout efficiency; plan and validate netlist mappings across dies, interposers, and substrates; define die placement, padstacks, net assignments, and package-level connectivity; create and maintain Package Requirement Documents (PRDs) detailing die arrangements, stackups, and design constraints
Seniority
Senior, hands-on IC
