Senior Staff Engineer, Physical Design
Core
Lead physical design and methodology for next-generation high-performance processor chips in leading-edge CMOS processes for server, 5G/6G, and networking applications.
Role type
Senior Staff Engineer, Physical Design
Builds
Custom Processor/ASIC solutions and data infrastructure IP
Domain
Semiconductor, Digital IC Design, Server/Networking Hardware
Deliverable
production ML models | product features
Required skills
Full-chip integration, Place and route, Static timing analysis, Physical verification, RTL to GDS flows, Digital logic, Computer architecture, Verilog, Scripting (Shell, Python, TCL)
Preferred skills
Multi-voltage design, Low-power design techniques, Cadence Innovus
Technologies
Cadence Innovus, EDA tools, Verilog, Python, TCL, Shell
Responsibilities
Collaborate with Digital/RTL/Analog teams for design convergence; Implement multi-voltage designs through place and route, static timing, and physical verification; Drive assembly and design closure with RTL teams; Provide technical direction and mentoring to junior staff; Write automation scripts in Shell, Python, and TCL.
Seniority
Senior Staff, hands-on IC with mentorship
