ASIC Physical Design Engineer II (Full Time) - United States
Core
Full RTL-to-GDSII implementation for advanced semiconductor nodes (sub-16nm to 3nm) to deliver high-performance networking chips.
Role type
Senior IC ASIC Physical Design Engineer
Builds
High-performance networking chips (Switching, Routing, Wireless)
Domain
Semiconductor / Networking Hardware
Required skills
RTL-to-GDSII implementation, hierarchical floor planning, place and route, clock and power distribution, static timing analysis (STA), timing convergence strategies, automated scripting, EDA tool usage, physical design lifecycle knowledge
Preferred skills
Python/Tcl/Perl scripting, industry-standard EDA tools (Cadence Innovus, Synopsys ICC2/Design Compiler), physical verification (DRC/LVS), static timing analysis tools (PrimeTime)
Technologies
Cadence Innovus, Synopsys ICC2, Synopsys Design Compiler, PrimeTime, Mentor Calibre, Synopsys ICV
Responsibilities
Own and drive RTL-to-GDSII implementation for advanced nodes; Define and execute hierarchical floor planning, place and route, clock and power distribution, and timing convergence strategies; Perform static timing analysis (STA), setup reviews, and sign-offs for multi-mode/multi-corner designs; Implement and manage timing ECO strategies; Analyze quality and efficiency gaps, recommend tool, flow, and methodology improvements; Collaborate with RTL, DFT, EDA vendors, and tool owners to drive design and implementation efficiency
Seniority
Mid-level IC Engineer
