Principal Engineer, Physical Design
Core
Architect and lead next-generation physical design methodologies and automation flows for high-performance processor chips in leading-edge CMOS processes.
Role type
Principal Engineer, Physical Design
Builds
Next-generation server, 5G/6G, automotive, and networking processor chips
Domain
Semiconductor / Custom Processor/ASIC / Physical Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
RTL-to-GDSII implementation, synthesis, floorplanning, place and route, clock tree synthesis, timing closure, static timing analysis, power/signal integrity analysis, EDA tool evaluation, Python scripting, Perl scripting, Tcl scripting, Makefile scripting, physical design methodology development
Preferred skills
EDA vendor partnership experience
Technologies
PrimeTime, Tempus, Voltus, RedHawk
Responsibilities
Architect and lead development of physical design methodologies and automation flows; Provide technical leadership in RTL-to-GDSII implementation; Serve as key technical advisor resolving complex implementation challenges; Collaborate with global cross-functional teams; Mentor and coach senior and junior engineers; Evaluate and drive adoption of emerging EDA tools; Represent the team in strategic technical discussions
Seniority
Principal, hands-on IC with strategic influence