Senior Staff Verification Engineer
Core
Architecting and developing functional verification environments, reference models, and bus-functional monitors for next-generation network switches and multi-core SoCs.
Role type
Senior Staff Verification Engineer (System Verilog/UVM)
Builds
Verification environments, test plans, and software tools for switching products and SoCs
Domain
Semiconductor / Hardware Verification / Networking
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
System Verilog, UVM, Python, Perl, C++, ARM assembly, Object-Oriented Design, Linux OS, networking protocols
Preferred skills
Random verification techniques, coverage analysis, debugging complex failures, tool development
Technologies
System Verilog, UVM, Python, Perl, C++, ARM assembly, Linux
Responsibilities
Develop architecture for functional verification environments; write verification test plans using random techniques and coverage analysis; develop tests and tune environments to achieve coverage goals; debug failures and resolve issues with designers; verify boot code and maintain tools for multi-core SoCs; unit and regression test software tools
Seniority
Senior Staff, hands-on IC
