Senior Principal Digital IC Design Engineer
Core
Design, develop, implement, verify, and document micro-architecture and RTL for complex power management integrated circuits used in high-speed interconnects for hyperscaler data centers.
Role type
Senior Principal Digital IC Design Engineer
Builds
High-performance mixed-signal ICs for data center interconnects
Domain
Semiconductor / Data Center Infrastructure / Digital IC Design
Required skills
Verilog/SystemVerilog, Synthesis, Static Timing Analysis (STA), Low Power Design, Perl/Python scripting, RTL linting, CDC analysis, Micro-architecture design, Register specification
Preferred skills
802.3 standards, Serdes design, Digital Signal Processing, Error Correction codes, Physical layer protocols
Technologies
Verilog, SystemVerilog, Spyglass, Perl, Python
Responsibilities
Design and verify micro-architecture and RTL for power management ICs; Collaborate with system architects on industrial quality implementations; Participate in full design cycle from spec to silicon bring-up; Mentor other digital design engineers
Seniority
Principal, hands-on IC design with mentorship
