Sr Staff Manager - Physical Design
Core
Architect and lead the development of next-generation physical design methodologies and automation flows for high-performance data processing silicon platforms.
Role type
Sr Staff Manager - Physical Design
Builds
Custom ASICs for Carrier, Cloud/Enterprise, and Automotive Compute market segments
Domain
Semiconductor / Physical Design / Digital Logic
Deliverable
production ML models | product features | infrastructure
Required skills
RTL-to-GDSII implementation, synthesis, floorplanning, place and route, clock tree synthesis, timing closure, memory generation, foundry process nodes (2nm, 3nm, 5nm), scripting (Perl, Tcl, Python), Verilog/VHDL, digital logic, computer architecture
Preferred skills
leading foundries, emerging EDA tools, cross-functional collaboration
Technologies
Perl, Tcl, Python, Verilog, VHDL, EDA tools
Responsibilities
Architect physical design methodologies, provide technical leadership in RTL-to-GDSII flows, work on complex Subsystem hardening, deliver reference floorplan and timing closed Sub System partitions, collaborate with DFT and SOC teams, serve as technical advisor, evaluate and drive adoption of EDA tools, represent team in strategic discussions, mentor engineers
Seniority
Sr Staff, hands-on IC with management responsibilities
