Link Layer architect
Core
Define and develop end-to-end link layer architectures for high-speed interconnects (Ethernet, custom link-layers, Die-to-Die) to enable next-generation datacenter products like SmartNICs, servers, and AI accelerators for hyperscalers.
Role type
Senior IC ASIC link layer architect
Builds
Custom silicon System in a Package (SiP) for datacenter clients
Domain
Semiconductor / Data Infrastructure / High-speed Interconnects
Deliverable
production ML models | product features | infrastructure
Required skills
Link layer architecture design, Ethernet protocols (IEEE 802.3 100G/200G), Error correction (FEC: Reed-Solomon, Hamming, BCH), Link training and equalization, SerDes/PHY interface understanding, System architecture definition, RTL design guidance, Cross-functional technical leadership
Preferred skills
Chiplet architectures, Advanced packaging, Industry standards organization involvement, Network protocol stack knowledge
Technologies
Ethernet, IEEE 802.3, SerDes, PHY, RTL, SiP
Responsibilities
Define link layer architectures for high-speed interconnects, Drive technical decisions on error correction and flow control, Create architectural specifications and design documents, Optimize link efficiency and bandwidth utilization, Engage with customers on architecture requirements, Mentor engineers and share expertise
Seniority
Senior, hands-on IC
