Interconnect and Compute Architect
Core
Define and build next-generation CPU networking architecture for high-performance datacenters and emerging robotics/automotive AI/ML applications.
Role type
Interconnect and Compute Architect
Builds
Next-generation CPU networking architectures for AI/ML workloads
Domain
Semiconductor hardware design, Datacenter networking, Robotics/Automotive
Deliverable
production ML models
Required skills
Ethernet network architecture, die-to-die interfaces, on-chip and off-chip fabric mapping, datacenter scale-up architectures (UALink, NVLink, Broadcom SUE), scale-out RDMA protocols (RoCE, Infiniband), forwarding, buffering, modeling, RTL design
Preferred skills
None stated
Technologies
RISC-V, Ethernet, UALink, NVLink, Broadcom SUE, RoCE, Infiniband
Responsibilities
Contribute to current datacenter networking efforts, seed and specify future medium- to low-power robotics/automotive devices, collaborate across hardware, software, and systems teams to define networking requirements, guide architectural decisions at the intersection of forwarding, buffering, modeling, and RTL design
Seniority
All levels considered
