Principal Silicon Design Engineer
Core
Designing high-performance, high-bandwidth System on Chip (SoC) architectures, RTL, and integration for AI and networking applications.
Role type
Principal Silicon Design Engineer (SoC/ASIC)
Builds
High-performance SoCs, IP blocks, and networking ASICs
Domain
Semiconductor, SoC Design, AI Hardware, Networking
Deliverable
production ML models | product features
Required skills
Microarchitecture specification, RTL coding (Verilog/System Verilog), Clock Domain Crossing (CDC), Lint closure, SoC integration, Synthesis, Timing constraints, PPA trade-offs, Post-Silicon Debug, Complex algorithmic design for AI, Script development
Preferred skills
Fabric/Network on Chip design, Complex Control Logic SoC Design
Technologies
Verilog, System Verilog
Responsibilities
Develop IP microarchitecture specifications, perform RTL design, integrate SoC including clocking and resets, execute synthesis and static checks (Lint, CDC), interact with architecture, verification, and physical design teams.
Seniority
Principal, hands-on IC
