Principal Silicon Design Engineer

India, Karnataka, Bangalore💼 Full-time🗓 2026-07-21 → 2026-07-31

Core

Designing high-performance, high-bandwidth System on Chip (SoC) architectures, RTL, and integration for AI and networking applications.

Role type

Principal Silicon Design Engineer (SoC/ASIC)

Builds

High-performance SoCs, IP blocks, and networking ASICs

Domain

Semiconductor, SoC Design, AI Hardware, Networking

Deliverable

production ML models | product features

Required skills

Microarchitecture specification, RTL coding (Verilog/System Verilog), Clock Domain Crossing (CDC), Lint closure, SoC integration, Synthesis, Timing constraints, PPA trade-offs, Post-Silicon Debug, Complex algorithmic design for AI, Script development

Preferred skills

Fabric/Network on Chip design, Complex Control Logic SoC Design

Technologies

Verilog, System Verilog

Responsibilities

Develop IP microarchitecture specifications, perform RTL design, integrate SoC including clocking and resets, execute synthesis and static checks (Lint, CDC), interact with architecture, verification, and physical design teams.

Seniority

Principal, hands-on IC

Rewrite

## About the role You will be part of the SOC design team driving many facets of high performance, high bandwidth designs. The tasks will include working on Intellectual Property (IP) microarchitecture specification, Register Transfer Level (RTL) design, System on Chip (SOC) integration including clocking and resets, Synthesis and static checks such as Lint and Clock/Reset domain crossings. Throughout the program you will be interacting with various teams, including architecture, verification, and physical design, ensuring that the design is implemented and verified to the spec. ## Requirements - 12+ years expertise in Digital Design including microarchitecture specification development, RTL coding in Verilog/System Verilog and Clock Domain Crossing (CDC)/Lint closure. - 6+ years of experience delivering successful IP or Application Specific Integrated Circuits (ASIC)/SOC designs. - 4+ years of experience in Synthesis, Timing constraints, Power, Performance, Area (PPA) trade-offs and Post-Silicon Debug. - 4+ experience in Designing Fabric/Network On Chip or Networking ASICs or Complex Control Logic SoC Design and Integration. - Clocking and reset. - Complex algorithmic designs for AI usages. - Script development. ## What we offer *(Content not provided in the original text)* ## About us *(Content not provided in the original text)*

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