Senior Staff Engineer, DFT
Core
Developing and integrating DFT architectures, flows, and methodologies for complex ASIC/SoC designs to enable customer requirements and ensure testability.
Role type
Senior Staff Engineer, Design for Test (DFT)
Builds
Custom and Compute Business SoCs with embedded test infrastructure
Domain
Semiconductor / VLSI / Digital IC Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Scan insertion and ATPG, MBIST/OCC validation, Hierarchical DFT and SDC constraints, IEEE 1687 IJTAG, SpyGlass DFT rules, Digital Circuit and Logic Design, RTL/Synthesis/STA/Physical Design flows, Scripting (TCL/Perl/Python/Shell), Silicon bring-up and debug
Preferred skills
None explicitly stated as preferred
Technologies
Synopsys, Cadence, Mentor, SpyGlass
Responsibilities
Develop and integrate scan, MBIST, OCC, boundary scan, and hierarchical SDC flows; Drive ATPG pattern generation, compression techniques, GLS, and retargeting; Collaborate with RTL, synthesis, and physical design teams; Perform SpyGlass DFT checks; Perform pre-silicon validation and support post-silicon bring-up; Optimize test methodologies for cost, coverage, and yield
Seniority
Senior Staff, hands-on IC
