Senior DFT Engineer
Core
Lead DFT architecture and implementation for complex mixed-signal SoCs to ensure high test coverage, manufacturability, and first-pass silicon success for high-power satellite platforms.
Role type
Senior Design-for-Test (DFT) Engineer
Builds
Mixed-signal System-on-Chips (SoCs) for high-power satellites
Domain
Aerospace / Semiconductor Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
RTL DFT insertion, ATPG flow development, scan chain insertion and optimization, memory BIST (MBIST) and logic BIST (LBIST), mixed-signal test strategies, low-power DFT methodologies, silicon debug and correlation, DFT verification and signoff
Preferred skills
IEEE 1149.x (JTAG/boundary scan) standards, multi-voltage domain DFT, SerDes or RF/mixed-signal SoC experience, physical design impact analysis, automation scripting
Technologies
ATPG tools, DRC/Lint checkers, gate-level simulation environments, mixed-signal test interfaces
Responsibilities
Define and implement DFT architecture for mixed-signal SoCs including scan, MBIST, LBIST, and boundary scan; Lead RTL-level DFT insertion, scan chain insertion and optimization, test point insertion, and low-power DFT methodologies; Own ATPG flow development and execution by generating high-quality stuck-at, transition, and path delay test patterns; Develop and integrate DFT strategies for mixed-signal blocks, including wrapper-based approaches, and analog test interfaces and BIST solutions; Collaborate with RTL, DV, and PD teams to ensure clean DFT integration at RTL and gate-level, and timing and physical constraints alignment; Drive DFT verification and signoff, including Scan/ATPG coverage metrics, DRC/Lint checks, gate-level simulation and pattern validation; Support bring-up and silicon debug activities by analyzing tester failures, yield issues, and ATPG pattern correlation with silicon behavior
Seniority
Senior, hands-on IC
