DFT Engineer
Core
Designing and implementing Design for Test (DFT) solutions for large, multi-core AI accelerator ASICs to ensure robust testing and yield.
Role type
DFT Engineer for AI accelerator ASIC
Builds
Test solutions and scan chains for multi-core AI accelerator SoCs
Domain
Semiconductor hardware design, AI accelerators, ASIC development
Deliverable
production ML models | product features | infrastructure
Required skills
DFT architecture, scan insertion, ATPG, memory BIST, EDA tools, Python/Tcl scripting, physical design collaboration, silicon bring-up/debug
Preferred skills
Advanced SoC design expertise, experience with large-scale ASICs
Technologies
EDA tools, Python, Tcl, ATE
Responsibilities
Contribute to DFT architecture of multi-core AI accelerator SoC; Drive integration of DFT tools into the EDA flow; Implement scan insertion, compression, and test logic; Generate and analyze ATPG patterns for structural faults; Support MBIST implementation for embedded memories; Work with physical design to ensure clean scan chain implementation and timing closure; Support silicon bring-up, debug, and test analysis; Work with test and product engineering teams to bring up and debug ATPG patterns on ATE, supporting production test and yield ramp
Seniority
Mid-level IC Engineer
