Staff DFT Engineer
Core
End-to-end ownership of DFT insertion, verification, DRC closure, and test coverage closure from RTL/netlist through post-silicon debug for complex SoC designs.
Role type
Staff DFT Engineer
Builds
Clean DFT signoff and robust test coverage for complex SoC designs
Domain
Semiconductor / Digital IC Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work -> infrastructure (DFT implementation & verification)
Required skills
MBIST/BISR insertion, Boundary Scan (IEEE 1149.x), IJTAG (IEEE 1687), Siemens Tessent, ATPG pattern generation, TCL scripting, DFT DRC resolution, scan timing constraints
Preferred skills
MBIST coverage optimization, post-silicon pattern bring-up, mixed-signal/SERDES DFT
Technologies
Siemens Tessent, SpyGlass, TCL
Responsibilities
Perform MBIST/BISR insertion and integration; Execute DFT verification and debug using Siemens Tessent; Generate and debug MBIST and logic ATPG patterns; Create and maintain TCL scripts for automation; Collaborate with RTL and Physical Design teams; Support pre-silicon signoff and post-silicon debug
Seniority
Staff, hands-on IC
