Design Verification Engineer, Principal
Core
Architect functional verification environments and lead verification teams for high-speed data transfer chips in network switching SoCs.
Role type
Principal Design Verification Engineer (Network Switching)
Builds
Functional verification environments, reference models, bus-functional monitors, and drivers for multi-core SoCs.
Domain
Semiconductor / Network Switching / SoC Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work -> product features (verification environments for chips)
Required skills
System Verilog, UVM, Python, Perl, C++, ARM assembly, Object-Oriented Design, Linux OS, random verification techniques, coverage analysis
Preferred skills
Networking protocols, EDA Verification tools
Technologies
System Verilog, UVM, Python, Perl, C++, ARM assembly, Linux
Responsibilities
Develop architecture for functional verification environments including reference models and monitors; Write verification test plans using random techniques; Debug failures and resolve issues with designers; Architect and maintain tools for multi-core SoC design; Lead verification engineers on project level; Unit and regression test software tools.
Seniority
Principal, hands-on IC with leadership
