Senior Digital Verification Engineer
Core
Develop and execute comprehensive verification plans for subsystem and SoC-level ASIC/SoC designs using scalable verification environments.
Role type
Senior IC digital verification engineer (ASIC/SoC)
Builds
Production ASIC/SoC chips
Domain
Semiconductor / Digital IC Design
Required skills
System Verilog, UVM, constrained-random testing, coverage-driven verification, debugging RTL/gate-level issues, scoreboards, monitors, protocol checkers, assertions (SVA), C/C++ golden models, fault injection simulation
Preferred skills
Gate-Level Simulation (GLS), AI-assisted engineering tools, regression infrastructure automation
Technologies
System Verilog, UVM, Xcelium, Questa, I2C, AHB/APB, MIPI
Responsibilities
Develop reusable verification environments; Create test cases (constrained-random, directed, scenario-based); Analyze and debug RTL and gate-level simulation failures; Collaborate with design, DFT, and physical design teams; Execute fault injection simulations; Work with AI-assisted tools to enhance verification automation
Seniority
Senior, hands-on IC
