Senior Design Verification Engineer
Core
Plan and execute verification of complex design IP, creating constrained-random environments and formal verification to ensure functional correctness before tape out.
Role type
Senior Design Verification Engineer (IC)
Builds
Production silicon chips (IPs, Sub Systems, SoCs)
Domain
Semiconductor / Hardware Verification
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
SystemVerilog, UVM, Formal Verification (SVA), C/C++, Functional Coverage, Debugging, Python/Ruby/Perl, VIP Integration, Pre-silicon verification
Preferred skills
AI tools for productivity, Leading verification from architecture to freeze, Cross-functional collaboration
Technologies
SystemVerilog, UVM, SVA, Python, Ruby, Perl
Responsibilities
Plan verification strategies for complex design IP interacting with architecture and design engineers. Create and enhance constrained-random verification environments using SystemVerilog and UVM. Develop tests using UVM or C/C++ and analyze/debug test failures with designers. Identify and write functional coverage for stimulus and corner cases to meet tape out requirements. Engage in chip bring-up activities and write test firmware. Drive innovation by enhancing validation efficiency through new methodologies and tools. Experience leading the verification of a design from architecture to freeze.
Seniority
Senior, hands-on IC
