Senior Principal Engineer, Physical Design
Core
Senior leader shaping long-term vision and strategy for physical design capabilities and infrastructure for next-generation high-performance processor chips in leading-edge CMOS processes.
Role type
Senior Principal Engineer, Physical Design (Strategy & Leadership)
Builds
Next-generation server, 5G/6G, and networking SoCs
Domain
Semiconductor / ASIC Physical Design
Deliverable
production ML models | product features | infrastructure
Required skills
Hierarchical physical design strategies, RTL-to-GDSII implementation, timing closure, power/signal integrity signoff, physical verification (DRC/LVS), team leadership, project management, automation scripting (Tcl/Python/Perl), EDA tool expertise
Preferred skills
AI/ML-driven optimization in physical design tools
Technologies
Tcl, Python, Perl, EDA tools, leading-edge CMOS processes
Responsibilities
Shape long-term physical design vision aligned with company strategy; Lead RTL-to-GDSII implementation for multiple SoC programs; Provide strategic leadership and technical direction to physical design teams; Mentor and develop engineering talent; Oversee team structure, hiring, and performance management; Drive development of next-generation physical design methodologies and automation; Manage project schedules, resources, and risk; Represent physical design function in executive discussions.
Seniority
Principal, strategy & mentorship