DFT Principal Engineer
Core
Lead Design for Test (DFT) strategies and execution for advanced networking ASICs to ensure reliability and testability across the full silicon lifecycle.
Role type
Principal DFT Engineer (ASIC VLSI)
Builds
High-performance networking SoCs and silicon bring-up
Domain
Semiconductor / ASIC Design / Networking
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
DFT methodologies (ATPG, MBIST, BScan, JTAG/iJTAG), SoC flows, silicon debug, EDA tools (Cadence, Synopsys), RTL design (Verilog/SystemVerilog), low power design, ASIC verification
Preferred skills
DFT specification and architecture definition, synthesis and simulation flows, managing multiple tasks
Technologies
Cadence, Synopsys, Siemens/Mentor Graphics, Verilog, SystemVerilog, JTAG, iJTAG, SCAN, MBIST
Responsibilities
Execute major DFX disciplines (ATPG, MBIST, DFX Verification, STA sign-off), act as DFX owner for projects, collaborate with SoC Architecture and Backend teams, lead DFT activities throughout ASIC development flow, perform silicon bring-up and debug
Seniority
Principal, hands-on IC with strategic ownership