Layout Engineer
Core
Lead analog layout engineering for IC projects, managing schedules, risk mitigation, and final layout quality while collaborating with design, packaging, and process teams.
Role type
Senior IC analog layout engineer (layout lead)
Builds
Analog and mixed-signal integrated circuits (ICs)
Domain
Semiconductor manufacturing / Analog IC design
Required skills
Analog and mixed-signal layout techniques, LVS/DRC/ERC debugging, Device Matching, Power Bus design, ESD/LU protection, Layout parasitics analysis, Semiconductor device physics, Virtuoso XL/Assura/PVS/Voltas tools, SKILL coding for automation
Preferred skills
Experience with 40nm–180nm nodes, BiCMOS technologies, Test vehicle development, Mentorship of junior engineers
Responsibilities
Frame layout schedules and risk mitigation plans, Collaborate with design and packaging teams to balance area/performance/schedule, Update PDK/P-cells and design rules, Analyze and close EM/thermal/ESD/parasitic issues, Develop test vehicles for new technologies, Mentor junior layout engineers
Seniority
Senior, hands-on IC
