Layout Engineer
Core
Develop and prepare multi-dimensional layouts and detailed drawings of semiconductor devices from schematics and geometry.
Role type
Senior IC layout engineer (analog/mixed-signal)
Builds
IC layouts for production, test vehicles for new process & package technology
Domain
Semiconductor manufacturing, IC design
Required skills
Full chip layout experience, LVS/DRC/ERC debugging, analog and mixed-signal layout techniques, layout parasitics analysis, device physics knowledge, semiconductor fabrication process knowledge, Virtuoso XL/Assura/PVS/Voltas proficiency, automation/SKILL coding
Preferred skills
Mentorship of junior engineers, process quality improvement initiatives, cross-talk and ESD/LU protection techniques
Technologies
Virtuoso XL, Assura, PVS, Voltas, 40nm, 65nm, 90nm, 130nm, 180nm, BiCMOS
Responsibilities
Frame layout schedules and risk mitigation plans, collaborate with design/packaging/process teams to balance area/performance/schedule, analyze and close Electro Migration/Thermal/ESD/LU performance, develop test vehicles for new technologies, mentor junior layout engineers, ensure final layout meets design expectations
Seniority
Senior, hands-on IC
