Senior Digital PD Engineer
Core
Senior Digital Physical Design Engineer responsible for end-to-end RTL-to-GDSII implementation, timing closure, and PPA optimization for high-speed mixed-signal communication circuits.
Role type
Senior IC Physical Design Engineer (Digital Backend)
Builds
High-performance custom ICs for mobile electronics (display power, chargers, PMICs, communication interfaces)
Domain
Semiconductor / VLSI Design / Mixed-Signal Communication
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
RTL-to-GDSII flow ownership, Static Timing Analysis (STA), Power/Performance/Area (PPA) optimization, DRC/LVS/ERC physical verification, floorplanning, placement, CTS, routing, clock/reset/DFT architecture analysis
Preferred skills
Mixed-signal co-design and floor planning, EDA flow scripting (Tcl/Python/Perl), DFT integration (scan/BIST), low-power techniques (multi-Vt/power gating), customer-facing technical authority
Technologies
Synopsys, Cadence, EDA tools, GDSII, RTL, Tcl, Python, Perl
Responsibilities
Own strategic direction of physical design methodologies and quality benchmarks; Lead end-to-end physical design lifecycle from floorplanning to signoff; Drive PPA optimization and timing/reliability closure; Mentor engineers and standardize implementation practices; Collaborate with EDA, Library, Memory, and IP teams to eliminate flow bottlenecks
Seniority
Senior, hands-on IC with strategic leadership