RET Layout/Mask Engineer
Core
Architecting new TI products by defining, designing, modeling, implementing, and documenting analog, digital, and RF integrated circuits (ICs) to enable high-volume manufacturing of 28nm process technologies.
Role type
Senior IC layout and mask engineer (computational lithography)
Builds
Production-ready IC layouts, test reticles, and measurement features for 28nm analog and embedded processing chips
Domain
Semiconductor manufacturing, computational lithography, resolution enhancement techniques (RET)
Deliverable
production ML models | product features | infrastructure
Required skills
EDA layout tools (Cadence, Synopsys), scripting (Python, SKILL, Perl), analog/digital/RF IC design, lithography process integration, OPC development, reticle measurement, automation development
Preferred skills
PDK development, PG flows, advanced lithography knowledge, cross-team collaboration
Technologies
Cadence suite, Synopsys, Python, SKILL, Perl
Responsibilities
Create layouts for lithography/etch wafer process setup, evaluation, and monitoring; Design and modify test features using design rules; Develop and implement automation for layout production; Collaborate with fabrication process engineering to determine specifications; Work with RET engineers on layout and floor plan of test reticles for OPC model calibration; Define specifications for reticle measurement and disposition; Create rules for layout placement with RET, scribe, and design teams
Seniority
Senior, hands-on IC