Senior ASIC Layout Engineer
Core
Design and verify high-performance standard cell libraries for next-generation ASICs on FinFET and GAA nodes, ensuring physical verification clean signoff and library quality from GDS to release.
Role type
Senior ASIC Layout Engineer (Standard Cell)
Builds
Standard cell libraries (logic, high-drive, clock, level shifter, tap/boundary, specialty) for Cisco Silicon One platform ASICs
Domain
Semiconductor / ASIC Design / Advanced Process Nodes (FinFET, GAA)
Required skills
Standard cell layout on advanced nodes (TSMC 5nm/3nm/2nm), Physical verification (DRC, LVS, antenna, ERC, extraction, EM/IR), Library QA (GDS, LEF, Liberty, NDM, CDL), Cadence Virtuoso proficiency, Automation scripting (Python, Tcl, SKILL)
Preferred skills
Analog/mixed-signal layout (PLLs, LDOs, bandgaps, IOs, sensors), Standard cell characterization and Liberty modeling, Library release (abstract/LEF, NDM, P&R tools), EM/IR closure, Low-power cells (multi-Vt, power gating), IO/bump cell layout
Technologies
Calibre, ICV, StarRC, Quantus, PrimeLib, Liberate, SiliconSmart, Innovus, Fusion Compiler, ICC2
Responsibilities
Drive layout architecture and design of standard cell libraries; Own physical design of complex cells optimizing for density, performance, power, EM, and manufacturability; Drive physical verification to clean signoff; Define and own library QA; Develop and deploy automation for layout, verification, and QA; Contribute to analog/mixed-signal IP design and layout; Lead block-level issue resolution and chip-level debug; Drive layout and QA reviews and mentor engineers
Seniority
Senior, hands-on IC with mentorship responsibilities
