ASIC DFT STA Engineer
Core
ASIC DFT STA Engineer responsible for timing constraint development, verification, and closure across implementation and post-silicon phases for next-generation networking chips.
Role type
Senior IC ASIC DFT STA Engineer
Builds
High-performance networking ASICs (Switching, Routing, Wireless)
Domain
Semiconductor / Networking Hardware
Required skills
Timing constraint development and verification, RTL design, CDC/RDC, SDC development, Scripting (Perl/TCL/Python/Makefile), DFT modes (scan shift/capture, BIST), STA tools (Synopsys TCM/Primetime), Synthesis tools (Fusion/design Compiler), Tessent DFT insertion
Preferred skills
PCIE timing constraints debugging, TSMC memory timing constraints, DFT mode timing closure, SDC debugging, Synopsys Fusion/design Compiler, Tessent DFT insertion
Technologies
Synopsys TCM, Synopsys Primetime, Synopsys Fusion, design Compiler, Tessent, Perl, TCL, Python, Makefile
Responsibilities
Develop and verify timing constraints (clock groups, exclusivity), lead DFT and quality process through implementation and post-silicon validation, debug timing constraints for DFT modes, collaborate on physical design signoff activities
Seniority
Senior, hands-on IC
