Design for Test Engineer - IC
Core
Design for Test (DFT) engineer implementing test strategies for 3nm and 5nm networking SoCs and IP blocks.
Role type
Senior IC Design for Test Engineer
Builds
Production silicon chips and IP blocks for networking and consumer applications
Domain
Semiconductor design, Networking, Consumer electronics
Required skills
Scan-insertion, ATPG, GLS, pattern simulation, MBIST insertion and verification, IEEE 1149.1 JTAG, RTL checking, Perl/Shell/TCL scripting, low power DFT
Preferred skills
Experience with multi-million gate count SoCs, Mentor Tessent, Synopsys Spyglass, VCS, Verdi
Technologies
Tessent, Spyglass, VCS, Verdi, Makefile
Responsibilities
Implement DFT for 3nm and 5nm networking chips and conduct IP DFT tasks, Carry out scan-insertion with Tessent TestKompress, Generate ATPG patterns in both compressed and uncompressed mode, Simulate patterns without and with timing for different corners, Debug mismatches using Verdi, Develop scripts in Perl, Shell, and TCL for DFT flow enhancement and automation, Insert and verify MBIST on relevant blocks, Conduct silicon debug and bring-up activities, Insert and verify IEEE 1149.1 JTAG
Seniority
Senior, hands-on IC (via careerplan.io/jobs/gad5bebd-design-for-test-engineer-ic-at-arrow-electronics-inc)
