ASIC DFT Technical Leader
Core
Lead Design-for-Test (DFT) strategy and implementation for next-generation networking ASICs, collaborating with RTL and physical design teams to drive quality from architecture through post-silicon validation.
Role type
Senior IC ASIC DFT Technical Leader
Builds
High-performance networking chips (Switching, Routing, Wireless) for Cisco's global infrastructure
Domain
Semiconductor hardware design / Networking infrastructure
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work -> infrastructure (ASICs)
Required skills
DFT architecture (Scan, BIST, Memory BIST, Boundary Scan), ATPG, JTAG protocols, EDA tools (TestMax, Tetramax, Tessent, PrimeTime), Gate-level simulation, VCS debugging, Post-silicon debug
Preferred skills
Verilog DFT logic development, DFT CAD development, Test Static Timing Analysis, System Verilog equivalence checking, Functional verification
Technologies
VCS, TestMax, Tetramax, Tessent, PrimeTime, JTAG, Scan, BIST
Responsibilities
Drive DFT requirements early in the design cycle with Front-end RTL and backend physical design teams; Lead DFT and quality processes through the entire Implementation flow; Execute post-silicon validation using DFT patterns; Participate in physical design signoff activities
Seniority
Senior, hands-on IC