DFT Lead
Core
Lead DFT strategy and execution for complex SoC and MCU designs targeting AI data center and humanoid system applications.
Role type
Senior IC DFT Lead
Builds
Test structures including scan chains, BIST, JTAG, boundary scan, and ATPG flows for silicon products
Domain
Semiconductor / Digital IC Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
DFT methodologies (scan insertion, ATPG, BIST, JTAG, boundary scan, test compression), SoC/MCU architecture, EDA tools (Synopsys TestMAX, Mentor Tessent), cross-functional team leadership, technical strategy formulation
Preferred skills
Embedded systems or MCU product development, silicon bring-up, failure analysis, yield improvement initiatives
Technologies
Synopsys TestMAX, Mentor Tessent
Responsibilities
Lead DFT strategy and execution across complex SoC and MCU designs; Direct and guide a team of DFT engineers in design and evaluation of test structures; Prepare and present outcomes of DFT projects and test coverage metrics; Collaborate cross-functionally with design, verification, physical design, and manufacturing teams; Drive continuous improvement in test coverage and fault detection; Select, develop, and evaluate personnel to ensure efficient operation of the DFT function
Seniority
Senior, hands-on IC with leadership
