ASIC Design Verification Eng II Full Time - United States
Core
Develop and verify ASICs for Cisco's core Switching, Routing, and Wireless products using simulation, emulation, and bring-up processes.
Role type
Senior IC ASIC Design Verification Engineer
Builds
Hardware platforms for data center solutions
Domain
Semiconductor / ASIC Design Verification
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
SystemVerilog, UVM methodology, Perl scripting, Python scripting, test bench construction, functional coverage, regression debugging
Preferred skills
Complex block/cluster verification, SoC top-level verification, Veloce/HAPS emulation, constrained random environments, SystemVerilog constraints/structures/classes
Technologies
SystemVerilog, UVM, Perl, Python, Veloce, HAPS
Responsibilities
Maintain and enhance existing DV environments; Construct test benches including scoreboards, agents, sequencers, and monitors; Write test plans and develop test cases; Debug regression failures and drive module verification closure; Ensure complete verification coverage through code and functional coverage review
Seniority
Mid-Senior, hands-on IC
