ASIC Engineering Technical Leader || Physical Design | Floor Planning | GSP & PD | Exp - 11+ years
Core
Lead physical design implementation for next-generation networking chips in advanced process nodes, driving the flow from RTL to GDS with focus on performance and die size optimization.
Role type
Senior ASIC Physical Design Technical Leader
Builds
Networking chips for data and infrastructure connectivity
Domain
Semiconductor / ASIC Physical Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Hierarchical floor planning, Place & Route, Timing closure, Power integrity analysis, Static timing verification, Physical verification, Equivalence checks, Large-scale design implementation (>100M gates), Advanced node technology (sub-16/14/7/5/3nm), Scripting (TCL, Shell, Perl, Python)
Preferred skills
Cadence Innovus, Synopsys ICC2, Synopsys DC/FC, Synopsys Formality, Cadence LEC, Primetime-DMSA, Apache Redhawk, Synopsys ICV, Mentor Calibre
Technologies
Cadence Innovus, Synopsys ICC2, Synopsys DC, Synopsys FC, Synopsys Formality, Cadence LEC, Primetime-DMSA, Apache Redhawk, Synopsys ICV, Mentor Calibre
Responsibilities
Analyze quality and efficiency gaps in physical design tools and flows; Drive methodologies to streamline and automate physical design work; Execute STA setup, convergence, and sign-off for Multi-Mode and Multi-corner designs; Develop and converge Timing ECO strategies using Tweaker/Primetime flows; Evaluate multiple timing methodologies and tools across different designs and technology nodes.
Seniority
Senior, hands-on IC with technical leadership
