ASIC DFT Engineer || DFT/ATPG/MBIST/SCAN/JTAG || 8+ years
Core
Implement Hardware Design-for-Test (DFT) features to support ATE, in-system test, debug, and diagnostics for next-generation network silicon architectures.
Role type
Senior ASIC DFT Hardware Engineer
Builds
Testable silicon chips for Cisco Silicon One™ programmable architecture
Domain
Semiconductor / Networking Hardware
Deliverable
production ML models | product features
Required skills
DFT IP development, JTAG protocols, Scan insertion, ATPG, EDA tools (TestMax, Tetramax, Tessent), Gate-level simulation, VCS debugging, Post-silicon validation, ATE patterns (P1687), Scripting (Tcl, Python, Perl)
Preferred skills
Test Static Timing Analysis, Post-silicon validation using DFT patterns
Technologies
VCS, TestMax, Tetramax, Tessent, P1687
Responsibilities
Implement DFT features for ATE and diagnostics; Develop innovative DFT IP for full chip integration; Collaborate with design/verification/PD teams for test logic validation; Debug and craft solutions with minimal mentorship
Seniority
Senior, hands-on IC
