DFT Technical Leader
Core
Lead Hardware Design-for-Test (DFT) features for next-generation networking chips, driving testability from RTL through post-silicon validation.
Role type
Senior IC ASIC Technical Leader (DFT)
Builds
Innovative silicon devices, bare die, and stacked die with integrated DFT and debug strategies
Domain
Semiconductor hardware design, networking chips, silicon engineering
Deliverable
production ML models | product features
Required skills
DFT architecture, ATPG, JTAG protocols, Scan and BIST, EDA tools (TestMax, Tetramax, Tessent, PrimeTime), Gate level simulation, ATE patterns, P1687
Preferred skills
Verilog DFT logic development, DFT CAD development, Test Static Timing Analysis, System Verilog equivalence checking
Technologies
VCS, TestMax, Tetramax, Tessent, PrimeTime, P1687
Responsibilities
Implement DFT features supporting ATE, in-system test, and diagnostics; Develop innovative DFT IP for full chip integration; Collaborate with RTL and physical design teams on test logic validation; Drive re-usable test strategies for new silicon models; Debug solutions with minimal mentorship
Seniority
Senior, hands-on IC
